PowerPC processors attempt to determine whether a conditional branch is likely to be taken or not. By default, its assumes the following about conditional branches:
If the assembly language programmer knows the likely outcome of a conditional branch, a suffix can be added to the mnemonic that indicates which way the branch should be predicted to go: a `+' instructs the processor to predict that the branch will be taken, while a `-' instructs it to predict that the branch will not be taken. Where an operator allows a prediction suffix, a `' symbol appears after it in the table in " See PowerPC Assembler Instructions ."
Use the jbsr pseudo instruction when you may not be able to reach the target of a branch and link instruction with a bl instruction. The jbsr instruction uses a sequence of code called a long branch stub which will always beable to reach the target.
jbsr _foo,L1
...
L1: lis r12,hi16(_foo) ; long branch stub
ori r12,r12,lo16(_foo)
mtctr r12
bctr
The jbsr pseudo instruction assembles to a bl instruction targeted at L1. It also generates a PPC_RELOC_JBSR relocation entry for the symbol _foo. Then when the linker creates a non-relocatable output file it will change the target of the bl instruction to _foo if the bl instruction's displacement will reach. Else it will leave the bl instruction targeted at L1.